Silent acknowledgement of routing in a mesh network

ABSTRACT

In embodiments of the present invention improved capabilities are described for sending a single cast frame from a first node to a second node in a mesh network; sending the single cast frame from the second node to a third node in a mesh network; using the first node to detect the single cast frame sent from the second node to the third node; and interpreting this detection within the first node as an acknowledgement of success in sending the single cast frame from the first node to the second node. An additional method described herein may send a second single cast from the second node to a third node in a mesh network, interpret detection of the second single class frame within the first node as an acknowledgement of success in sending the first single cast frame from the first node to the second node.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.13/525,491 filed Jun. 18, 2012, which is a continuation of U.S.application Ser. No. 11/681,417 filed Mar. 2, 2007 (now U.S. Pat. No.8,219,705 issued Jul. 10, 2012), which is a continuation-in-part ofcommonly owned U.S. application Ser. No. 11/456,029 filed on Jul. 6,2006, and is a continuation-in-part of commonly owned U.S. applicationSer. No. 11/425,917 filed on Jun. 22, 2006, which claims benefit of thefollowing commonly-owned U.S. Provisional Patent Applications: App. No.60/763,835 filed on Jan. 31, 2006; App. No. 60/764,394 filed on Feb. 1,2006; App. No. 60/765,810 filed on Feb. 7, 2006; and, App. No.60/772,089 filed on Feb. 10, 2006. Each of the foregoing applications isincorporated herein by reference in its entirety.

FIELD OF INVENTION

The invention herein disclosed generally refers to wireless networks,and specifically to methods and systems for silent acknowledgement of arouting in a mesh network.

BACKGROUND

Wireless communication networks have limitations when used for buildingautomation. Structural barriers that deflect or cause the radiofrequency signals of wireless networks can prevent timely transmissionon the network. Introduction of noise sources from other radio frequencysources contribute to a reduction in quality and reliability. However,wiring building automation devices is very costly and intrusive, whileseverely limiting in flexibility and expandability.

Therefore there exists a need for a robust communication network forbuilding automation that overcomes the problems associated with wirelessnetworks without the high costs and inconvenience of wired networks.

SUMMARY

In embodiments, the present invention provides a method and system forsending a single cast frame from a first node to a second node in a meshnetwork; sending the single cast frame from the second node to a thirdnode in a mesh network; using the first node to detect the single castframe sent from the second node to the third node; and interpreting thisdetection within the first node as an acknowledgement of success insending the single cast frame from the first node to the second node.

In embodiments, a second single cast frame may be sent from the secondnode to a third node in a mesh network, and detection of the secondsingle cast frame by the first node interpreted as an acknowledgement ofsuccess in sending the first single cast frame from the first node tothe second node.

In embodiments, a single cast frame may be a routed single cast frame.It may be routed based at least in part on a routing table.

In embodiments, a single cast frame may be related to a metadata, acommand, or some other form of data. A command may relate to includingand or excluding a node in a mesh network, to enabling a securityfunctionality, to a communication speed, to a communication channel, toa communication channel availability, to a network security level, to anetwork topology, to a network routing strategy, or some other commandtype.

In embodiments, a network mandated speed may be 9.6 kbps, 40 kbps, 100kbps, or some other communication speed.

In embodiments, a communication channel availability may be associatedwith a single channel or a plurality of channels.

In embodiments, a network security level may be high, medium, low, orsome other network security level.

In embodiments, a single cast frame may be routed over a mesh networktopology that is an automation system network for controlling a device.A device may be a plurality of devices. In embodiments, the mesh networktopology may be implemented within a home. A home mesh network topologymay be related to an audiovisual system, such as an audiovisual systemincluding an entertainment device. An entertainment device may be atelevision, a signal conversion device, a DVR, a networked device, aUPnP networked device, a satellite receiver, a cable converter, a VCR, adigital video disc player, a video accessory, an audio amplifier, anaudio tuner, an audio amplifier-tuner combination, a CD player, a DVDplayer, a high definition DVD player, an audio cassette player, adigital audio tape player, an audio equipment, an equalizer, aphonograph player, a video component, a streaming media player, an mp3player, an audio file player, and audio component, an audio-visualcomponent, or some other entertainment device.

In embodiments, the mesh network topology may be related to a securitysystem. A security system may include an alarm, a lock, a sensor, adetector (such as a motion detector), or some other security systemcomponent.

In embodiments, the mesh network may be a wireless mesh network.

In embodiments, a node within the mesh network may be a multi-speednode.

These and other systems, methods, objects, features, and advantages ofthe present invention will be apparent to those skilled in the art fromthe following detailed description of the preferred embodiment and thedrawings.

BRIEF DESCRIPTION OF FIGURES

The invention will be more fully understood by reference to the detaileddescription, in conjunction with the following figures, wherein:

FIG. 1 illustrates a mesh network which includes a number of networknodes;

FIG. 2 illustrates a schematic of mesh network and node controlsoftware;

FIG. 3 shows an example of a type of re-transmission hand shaking;

FIG. 4 shows an example of a type of re-transmission hand shaking;

FIG. 5 shows how simultaneous communication to even a small number ofnodes impacts communication on a mesh network;

FIG. 5A shows an inclusion controller used to include a new slave onbehalf of the network SIS.

FIG. 6 shows software components of a mesh network split into a slaveapplication and basis software;

FIG. 7 shows controller node software features;

FIG. 8 shows a block diagram of the a mesh network node;

FIG. 9 illustrates a block diagram of a transceiver and RF modem;

FIG. 9A and FIG. 9B are waveforms of asymmetric modulation;

FIG. 9C is a block diagram of the Phase-Lock-Loop functionality of theinvention;

FIG. 9D is a timing diagram of the sequence for frequency calibration;

FIG. 9E is a waveform of VCO automatic self-calibration; and

FIG. 10 illustrates a timing diagram of a pulse width modulated output(PWM);

FIG. 11 shows I/O for a typical application circuit;

FIG. 12 shows external crystal connections;

FIG. 13 shows a simplified block diagram of an internal reset circuit;

FIG. 14 shows the RF connections in a typical application;

FIG. 15 shows a typical RS232 UART application circuit;

FIG. 16 gives a waveform of a serial byte;

FIG. 17 shows external interrupts;

FIG. 18 shows a simplified Triac application circuit;

FIG. 19 shows typical Triac waveforms;

FIG. 20 shows zero cross detection disturbed by noise;

FIG. 21 shows a masking of zero cross detection;

FIG. 22 shows the timing of a zero cross detect output;

FIG. 23 shows Triac fire delay from zero cross detect;

FIG. 24 shows Triac fire delay of FIG. 23 with a correction period;

FIG. 25 illustrates an overview of the internal ADC block;

FIG. 26 shows two registers connected as one distributed shift register;

FIG. 27 shows a typical interface application of an EEPROM;

FIG. 28 illustrates a simplified block diagram of a typical interface toprogramming equipment;

FIG. 29 illustrates a multi-speed demodulator.

FIG. 30 illustrates the potential relations between a media server,media renderer, and control point.

FIG. 31 illustrates a simplified embodiment of a media server, mediarenderer, and control point combination within a home audio-visualsystem.

FIG. 32 illustrates a simplified embodiment of silent acknowledgement ofa single cast frame routed over a mesh network.

FIG. 33A illustrates a simplified embodiment of dynamic enablement of asecondary channel selection.

FIG. 33B illustrates a simplified embodiment of the use of a preambleduring a dynamic enablement of a secondary channel selection.

DETAILED DESCRIPTION

The present invention relates to a reliable and low-cost control andmonitoring technology which enables embedded intelligence and wirelesscommunication for a variety of residential and light commercialapplications such as lighting and appliance control, automated meterreading, thermostat and ventilation control, security, and residentialgateway connectivity. In embodiments, a mesh network node may transformany stand-alone device into an intelligent networked device that may becontrolled and monitored wirelessly. The mesh network delivers highreliability networking at a fraction of the cost of other technologiesby focusing on narrow bandwidth applications and substituting costlyhardware with innovative software solutions such as frameacknowledgement, retransmission, collision avoidance, frame checksum,and sophisticated routing algorithms to assure full home coverage.

One of the key features of the mesh network technology is the routingcapability of all the nodes in the network. The mesh networkautomatically routes the signal from one node to the next therebyextending the range. Rather than depending solely on line-of-sightcommunications like other technologies, the mesh network is able to getaround obstacles by routing commands through other device-nodes in thenetwork when required. The mesh network technology also minimizes noiseand distortion problems caused by architectural obstacles and radio deadspots using innovative transmission techniques such as 2-wayacknowledgement and alternative route seeking.

For example, FIG. 1 illustrates a mesh network 100 which includes anumber of network nodes. The user may command a light associated withNode1 100A in a garage to turn off from Node4 100F in a master bedroom.If the direct transmission to Node1 100A is blocked by some RadioFrequency (RF) obstruction 102 (e.g. a stainless steel refrigerator in akitchen) Node4 100F automatically selects an alternate route, such asthrough Node3 100C (e.g. a thermostat in a hallway), rerouting as manytimes as is necessary to complete delivery of a command. Anacknowledgement is then sent back to Node4 100F confirming that thecommand has been executed by Node1 100A.

The mesh network infrastructure is decentralized, with nodes running asboth client and as repeater to avoid central points of failure andcontrol. Every new component that is added to the network increases pathredundancy and reliability, with the degree of redundancy and signalstrength increasing as a function of node density. If the distancebetween nodes is decreased by a factor of two, the resulting signal isat least four times more powerful at the receiver.

A mesh network is also self-organizing and doesn't require manualconfiguration. Because of this, adding new equipment or relocatingexisting equipment may be as simple as plugging it in and turning it on.The network discovers the new node and may automatically incorporate itinto the existing system. The mesh network technology may provide vastlyimproved area coverage and reliability with virtually unlimited range.

Referring to FIG. 2, mesh network software 200 may be designed onpolling of functions, command complete callback function calls, anddelayed function calls. Software 200 may be split into two groups ofprogram modules: basis software and application software. Basis softwaremay include system startup code, low-level poll function 222, main pollloop 202, protocol layers 204, and memory and timer 224 servicefunctions. Application software may include application hardwareinitialization 210 and software initialization 212 functions,application state machine 214, command complete callback functions 218,and a received command handler 220 function. The application softwaremay also include hardware drivers.

Main loop 202 may call a list of protocol functions. Functions may bedesigned to return to the caller as fast as possible to allow theCentral Processing Unit (CPU) to do other tasks. It is possible toreceive data, transfer data via the Universal Asynchronous ReceiveTransmit (UART) and check user-activated buttons simultaneously.

When the application layer 208 requests a transmission of data toanother node in network 100, the protocol layer may add a frame headerand a checksum to the data before transmission. The protocol layer mayalso handle frame retransmissions, as well as routing of frames throughrepeater nodes to nodes that are not within direct RF reach. When theframe transmission is completed an application specified transmitcomplete callback function 218 may be called. The transmission completecallback function 218 may include a parameter that indicates thetransmission result.

Application layer 208 may provide the interface to the communicationsenvironment which is used by the application process. The applicationsoftware may consist of the following functions: the hardwareinitialization function 210, software initialization function 212,application state machine 214, command complete callback functions 218,and a receive command handler function 220. The application implementscommunication on the application level with other nodes in network 100.At the application level may be a framework defined of device andcommand classes to obtain interoperability between mesh network enabledproducts from different vendors. The basic structure of these commandsmay provide the capability to set parameters in a node and to requestparameters from a node responding with a report containing the requestedparameters.

Wireless communication is by nature unreliable because a well definedcoverage area simply does not exist since propagation characteristicsare dynamic and unpredictable. The mesh network protocol may minimizenoise and distortion problems by using a transmission mechanism that mayinclude two re-transmissions to ensure reliable communication. Inaddition, single casts are acknowledged by a receiving node so theapplication is notified about how the transmission went.

FIGS. 3 and 4 show examples of this type of re-transmission hand shakingThe mesh network protocol may be designed to trade low latency at theexpense of handling simultaneously communication to a number of nodes inthe network. To obtain this the number of random backoff values islimited to 4 (0, 1, 2, and 3).

FIG. 5 shows how simultaneous communication to even a small number ofnodes 100 may block the communication completely. Simultaneouscommunication to nodes in the network which require a response from thenodes in question should therefore be avoided in the application.

From a protocol point of view there may be many different types ofnodes, for example: Control nodes, Static Controller nodes, InstallerController nodes, Controller bridge nodes, Slave nodes, Routing Slavenodes, and Enhanced Slave nodes. Controller nodes may store informationabout other nodes in the network. The node information includes thenodes each of the nodes can communication with (routing information).The Installation node may present itself as a Controller node, which mayinclude extra functionality to help a professional installer setup,configure, and troubleshoot a network. The Controller bridge node maystore information about the nodes in the network and in addition it maygenerate Virtual Slave nodes. A virtual Slave node is a node residing onanother network accessible through the bridge.

A network may consist of slaves, a primary controller, and secondarycontrollers. New nodes may be added and removed to or from the networkby using the primary controller. This may cause secondary controllersand routing slaves to malfunction if, for instance, a preferred repeaternode is removed. Without automatic network updating a new replicationhas to be made from the primary controller to all secondary controllers,routing slaves should also be manually updated with the changes. Innetworks with several controller and routing slave nodes, this couldcause difficulties the process is not automated. To automate theprocess, an automatic network update scheme may be included in thenetwork protocol. To use this scheme a static controller could beavailable in the network. This static controller may be dedicated tohold a copy of the network topology and the latest changes that haveoccurred to the network. The static controller used in the automaticupdate scheme is called the Static Update Controller (SUC).

Each time a node is added, deleted or a routing change occurs, theprimary controller may send the node information to the SUC. Secondarycontrollers may then ask the SUC if any updates are pending. The SUC maythen in turn respond with any changes since last time this controllerasked for updates. On the controller requesting an update may be calledto notify the application that a new node may have been added or removedin the network. The SUC may hold a large number of changes of thenetwork. If a secondary controller requests an updated after more thanthe maximum changes occurred, then it may not get updates and therequest may fail. In this situation a manual replication from theprimary controller may be necessary to update information on thesecondary controller. Routing slaves may have the ability to requestupdates for its known destination nodes. If any changes have occurred tothe network, the SUC may send updated route information for thedestination nodes to the Routing slave that requested the update. TheRouting slave application may be notified when the process is done, butmay not get information about changes to its routes. Routing slaves mayhave the ability to request updates for its known destination nodes. Ifany changes have occurred to the network, the SUC may send updated routeinformation for the designation nodes to the Routing slave thatrequested the update. The Routing slave application may be notified whenthe process is done.

A network can optionally have a SUC with enabled node ID serverfunctionality (SIS). The SIS enables other controllers toinclude/exclude nodes in the network on its behalf. This makes it easierto install complex networks because multiple controllers supportinclusion of nodes instead of one dedicated primary controller.

The SIS is the primary controller in the network and it has the latestupdate of the network topology and capability to include/exclude nodesin the network. Further, it is safer to keep the latest network topologyon the SIS (static controller) than a portable primary controller usedextensively during network installation. In embodiments, a network maycontain only one SIS. A primary controller can instruct a SUC to enablethe node ID server functionality (SIS). In case the SUC is primary thenthe SUC application can enable the node ID server functionality locally.

When including additional controllers to a network containing a SIS theymay become inclusion controllers and as such they may obtain thecapability to include/exclude nodes in the network on behalf of the SIS.Both portable and static controllers can be inclusion controllers. Theinclusion controller's network topology data may be dated from last timea node was included or the last time it requested a network update fromthe SIS and therefore it may not be classified as a primary controller.

FIG. 5A shows an inclusion controller 510 used to include a new slavenode 520 on behalf of an SIS 530. Inclusion controller 510 performingthe inclusion may first request the latest network topology changes 540and a free node ID 550 from SIS 530. Inclusion controller 510 mayreceive node information and range information 560 from newly includedslave 520 and may forward such information 570 onto SIS 530. Inembodiments, inclusion controller 510 may be within direct range of thenode to include.

A failing node may be replaced with a node inheriting the node ID fromthe failed node. Thereby the user avoids updating nodes havingassociations to the failed node. Associations within the failed node maybe re-established in the new node.

Software components of a system according to the present invention mayallow a routing slave to extend to a particular number of destinations(e.g. five) having return routes in very low latency applications. Inembodiments a routing slave may need to support more than the particularnumber of destinations and this may require the controller to supportfavoring return routes for destinations out of direct range with therouting slave. In embodiments, software components may enable acontroller to determine if two nodes are within direct range. A routingslave can request new return route destinations from the SUC/SIS node incase the available return routes fails. Furthermore the routing slavecan check if a node ID is within direct range in any of the existingreturn routes.

A software component may be used to cancel ongoing routing attempts.This software component can be used to abort a transmission to amalfunctioning node, thereby eliminating a large amount of routingattempts in a large network.

The software components of a mesh network controller may be split intothe controller application and the controller basis software, which mayinclude the mesh network protocol layers and control of the various datastored into memory. Controller nodes may include an external memory inwhich the application data area may be placed. The controller node mayhave a unique home ID number assigned, which may be stored in the basisarea of memory. When the new slave nodes are registered to the meshnetwork, the controller node may assign the home ID and a unique node IDto the slave node. The slave node may store the home ID and the node ID.When a controller is primary, it may send any network changes from theSUC node. The use of macros while developing application software mayallow adjustments to the interface without changing the applicationsource files.

The software components of a mesh network static controller node may besplit into a static controller application and the static controllerbasis software, which may include the mesh network protocol layers andcontrol of the various data stored into memory. The difference betweenthe Static Controller Node and the Controller Node is that the staticcontroller may not be powered down, that is it may not be used forbattery-operated devices. The static controller may have the ability tolook for neighbors when requested by a controller. This ability may makeit possible for a primary controller to assign static routes from arouting slave to a static controller. The static controller may be setas a SUC node, so it may send network topology updates to any requestingsecondary controller. A secondary static controller not functioning asSUC may also request network topology updates.

The software components of a mesh network installer controller may besplit into an installer controller application and static controllerbasis software, which includes the mesh network protocol layer. Theinstaller controller may be a mesh network controller node, whichincorporates extra functionality that may be used to implementcontrollers especially targeted towards professional installers whosupport and setup a large number of networks.

The software components of a mesh network controller bridge node may besplit into a controller bridge application and basis software, which mayinclude the mesh network protocol layer. The controller bridge node maybe a mesh network static controller node, which incorporates extrafunctionality targeted for bridging between the mesh network and othernetworks.

The software components of a mesh network slave node may be split into aslave application and basis software, which may include the mesh networkprotocol layer. Slave nodes may have a block of memory reserved forstoring data, and may have limited direct access to the block. The homeID and node ID of a new node may be zero. When registering a slave nodeto a mesh network the slave node may receive home and node ID from thenetworks primary controller node. These ID's may be stored in the basisdata area in memory. The slave may send unsolicited broadcasts andnon-routed singlecasts. Further it may be able to respond with a routedsinglecast (response route) in case another node has requested this bysending a routed singlecast to it. A received multicast or broadcast mayresult in a response route without routing.

FIG. 6 shows how the software components of a mesh network routing slavenode may be split into a slave application and basis software, which mayinclude the mesh network protocol layer. Routing slave nodes have ablock of memory reserved for storing data, and may have limited directaccess to the block. The mesh network basis software may reserve thefirst part of this area, and the last part of the area may be reservedfor the application data. The home ID and node ID of a new node may bezero. When registering a slave node to a mesh network the slave node mayreceive home and node ID from the network's primary controller node.These ID's may be stored in the mesh network basis data area in memory.The routing slave may send unsolicited broadcasts and single casts(routed or non-routed). Further it may respond with a routed singlecast(response route) in case another node has requested this by sending arouted singlecast to it. A received multicast or broadcast results in aresponse route without routing.

FIG. 7 shows how the enhanced slave node may have the same basicfunctionality as a routing slave node, but because it may have morefeatures on the hardware, more software components may be available.Enhanced slave nodes may have an external memory and a Real-Time Clock(RTC) 700 and Wake-Up Timer (WUT) 824. The basis software may reservethe first area of external memory, and the last area of external memorymay be reserved for the application data.

An internal ring oscillator is used as a base for a wake up timer. Theoscillator has a very low power consumption but is highly dependant ontemperature, supply voltage and process variation. In order tocompensate for the high variation a calibration circuit is built intothe chip. The calibration circuit measures the oscillation frequencyagainst the system clock and derives a calibration constant. As the ringoscillator runs at several kHz the calibration is as fast compared towake up period. The calibration is performed automatically beforeentering WUT mode (wake up timer mode).

A node in mesh network 100 may be implemented with a single integratedcircuit (e.g. an IC, ASIC, FPGA, etc.). FIG. 8 shows a block diagram ofthe a mesh network node, which may consist of many sub-components suchas an integrated RF transceiver 802, an 8051 Microcontroller Unit (MCU)830 with Random Access Memory (RAM) 832, mesh network softwareApplication Programming Interface (API) 828, and memory storage for userapplication software 828 such as Flash memory. In addition to thesemajor functional blocks a single chip implementation may contain anAnalog-to-Digital Converter (ADC) 822, general purpose Input/Output(I/O) pins 808, Power-On Reset (POR) circuit/brown-out detector 812,Triac controller 820, Serial Peripheral Interface (SPI) 824, interruptcontroller, and UART 814 serial interface for connecting to peripheraldevices. Such a device may be designed for very low power and lowvoltage applications and highly optimized for battery-poweredapplications and easy integration to products with demanding sizeconstraints.

Supply regulators 834 regulate the external supply down to a lowinternal voltage supply. Supply regulators 834 may significantly improvesupply noise tolerance of the chip.

A single chip implementation of the embodiment of FIG. 8 may run on asystem clock that is derived from an XTAL. For example, clock control810 divides an external crystal (not shown) into two internal clocks. Inthe preferred embodiment of FIG. 1, an external crystal of either 16 MHzor 32 MHZ would allow clock control 810 to generate an 8 MHz clock forRF circuits and a 16 MHz clock for MCU 830 and peripherals.Alternatively, clock control 810 may interface to an external crystalcontrolled oscillator.

The POR circuit 812 may eliminate the need for external reset circuitry,holding reset during power-on and brown-out situations. POR 812 may bedesigned with glitch immunity and hysteresis for noise and transientstability. POR 810 circuit may have extremely low power consumption andis active even in a sleep mode.

Referring further to FIG. 8 and FIG. 9, a transceiver 802 may be able totransmit and receive Manchester coded data 9.6 kbits. FIG. 9 shows theinvention communicating NRZ coded data at approximately 40 kb/s. RFtransceiver 802 may handle all the RF related functions such asManchester encoding/decoding 900, pre-ample detection andserialization/deserialization. The output power of the transmitter PowerAmplifier 902 may be adjustable in steps of 2 dB. The different parts ofthe RF transceiver 802 may be powered up and down so only the requiredcircuits may be powered at a time. The RF transceiver 802 may only needexternal components for input and output matching. A block diagram ofthe Transceiver 802 including RF modem 842 is given in FIG. 9.

Transceiver 802 includes multiple parallel receive demodulators, eachfor detecting a different received communication signal frequency,enabling the single chip embodiment to operate in an environment with aplurality of communication signal frequencies as may occur in networksof current and older technology devices, and/or different types ofdevices. The multiple demodulators are configured to receive outputsignals from RF transceiver 802 interface, allowing the firstdemodulator that detects a valid signal to take control, thustransparently receiving a signal at any of a plurality of supported datarates, without prior negotiation with an external device. Nocommunication overhead results from supporting multiple receive datafrequencies, allowing fast reception of unsolicited transmissions fromunknown sources.

An auto-speed receiver may include feeding the output of one radiofront-end to multiple demodulators, each for a different data rate, andthen allowing the first demodulator detecting a valid signal to takecontrol, thus transparently receiving a signal at any of the supporteddata rates without prior negotiation. This results in benefits includingno overhead from using multiple data rates, and fast reception ofunsolicited transmissions from unknown source without overhead of datarate negotiation.

The solution provides seamless installation of nodes only supportingmulti-speed nodes (e.g. 9.6 kbps and 9.6/40 kbps) in the same network.The transceiver 802 is used to detect speed (e.g. 9.6/40 kbps) of theframes received to make a speed independent receiver. In embodiments, anoptimal speed (e.g. fastest speed) to the destination node may be known(e.g. through testing and storing of information in association with arouting table) and a transmitting node may transmit at the optimalspeed.

The transmitter side may use a method where the highest known speed thatcan be used to reach the end destination will be used. In embodiments, acontroller may send a multicast frame using the optimal speed. Forexample, if a transmitter knows all destination nodes of a multicastframe supports 40 kbps, the transmitter will transmit the multicast at40 kps. As a further example, to ensure all nodes within direct range ofa transmitter receive a broadcast frame, a transmitter will send a thebroadcast frame at 9.6 kbps

A transmitting controller may select a specific route of nodes for asingle cast or a routed single cast frame based on the route comprisingonly nodes which support a preferred transmission speed. For example, ifa transmission controller can determine a route of nodes in which allthe nodes support 40 kbps, the controller may select this route for arouted single cast frame. Alternatively if such a route cannot bedetermined, the controller will transmit at the optimal speed for anyroute. Continuing the example of above, in such a route the controllerwould transmit a single cast or routed single cast frame at 9.6 kbps.

Likewise the controller may try to achieve the highest possible speedwhen assigning return routes to a routing slave. Since a routing slavemay store the speed for each route to a destination, a routing slave canhave a mixed set of stored speeds (e.g. 40 kbps and 9.6 kbps) for routesto each destination.

A node information frame or a transfer presentation frame may be sentout at a low speed (for example 9.6 kbps) to allow nodes that supportonly the low speed, or nodes that support a plurality of speeds, to beincluded/excluded by the controller.

In embodiments, channel selection may be dynamically performed locallyon each node without need of distributing network information, norrequiring user intervention. Dynamic channel selection may not requireadditional installation steps. The dynamic nature may also enable thenetwork to maximize the usage of free communications slots on theavailable channels. The nodes in the network may listen on the availablechannels based at least in part on a predefined algorithm (e.g., limitedto round robin). A node may select a next communication channel, andstay on each selected channel for a predefined duration. The node maystay on the selected communication channel and receive messages. Oncethe node is ready to receive new frames, it may once again select a nextcommunication channel and repeat the process.

In embodiments, a communication channel may have multi-speedcapabilities within a single carrier frequency, and/or it may havemulti-speed capabilities across multiple carrier frequencies.

In embodiments, a node in a mesh network may be used to perceive aplurality of channels within a mesh network. A node may select a firstchannel from the plurality of channels within the mesh network andremain on the first channel for a predefined duration. If during thepredefined duration, a signal is not detected, the node may select asecond channel and remain on the second channel for predefined durationin order to detect a signal. If during the predefined duration ofremaining on the first channel a signal is detected, the node may remainon that channel beyond the predefined duration in order to receive amessage. The node may then select a second channel once the message onthe first channel is received. This process of channel selection mayinclude a plurality of nodes and or a plurality of channels within amesh network.

An aspect of the present invention relates to a portable node (e.g.portable mesh node) where the portable node may be associated with auser interface or other device. The portable node may be similar toother nodes as described herein and it may communicate to and from thenetwork either directly to a master controller or through other nodes inthe mesh network. The portable node may be discoverable as other nodesare discoverable. For example, the portable node may be located by othernodes sending ‘find’ requests to the portable node. Once the portablenode receives a find request, it may respond and a communication linkand hand-offs to other nodes in the network may then be completed. Inother embodiments, the portable node may be programmed to send ‘find’identifiers periodically. For example, the portable node may send a datapacket to all nodes in the area (i.e. within its range) and the nearbynodes may identify that they can communicate with the portable node. Inother embodiments, the surrounding nodes may be used to physicallylocate the portable node through triangulation techniques or the like.

Software components of a system according to the present invention mayinvolve interfacing with or otherwise controlling streaming data withina network. For example, a user interface may be associated with theportable node and it may be adapted to scan through a set ofentertainment titles (e.g. music titles, video titles, movie titles) toselect a title to play on an entertainment device (e.g. audio/videoequipment) controlled by another node in the network. The entertainmentsystem may provide functionality similar to known high end mp3 playersfor example. In embodiments, an entertainment device may be atelevision, a signal conversion device, a DVR, a networked device, aUPnP networked device, a satellite receiver, a cable converter, a VCR, adigital video disc player, a video accessory, an audio amplifier, anaudio tuner, an audio amplifier-tuner combination, a CD player, a DVDplayer, a high definition DVD player, an audio cassette player, adigital audio tape player, an audio equipment, an equalizer, aphonograph player, a video component, a streaming media player, an mp3player, an audio file player, and audio component, an audio-visualcomponent, or some other entertainment device.

In embodiments, information relating to entertainment devices and/orentertainment media may be distributed through a mesh network in a datastructure. A data structure may include metadata. In embodiments,metadata may be related to an image, a photo, audio, a music track, anaudio broadcast, an audio book, a video, a movie, a video broadcast, astored video, a live video, a digital video recorder file, a musicvideo, audio-visual equipment, an appliance, a content directory, andother metadata types. Metadata may be a description of content beingdelivered, a rating, a title, a music title, a movie title, a publisher,a right, a plurality of rights, a genre, a language, a relation, aregion, a radio call signal, a radio station, a radio band, a channelnumber, an image name, an artist name, a music track, a playlist, astorage medium, a contributor, a date, a producer, a director, a DVDregion code, a channel name, a scheduled start time, a scheduled endtime, an icon, and the like.

In embodiments, such as that illustrated in FIG. 30, a media server 3000may provide entertainment content (e.g., video, song, image, etc.) andmay provide the content to a media renderer 3002. A media renderer 3002may be capable of rendering entertainment content provided by a mediaserver 3000. A media renderer 3002 may be identified with an endpointidentifier that is unique to a media renderer 3002. A control point 3004may coordinate the operation of a media server and media renderer 3002.For example, through a control point, an end-user may be able to selectwhat they want to view and/or hear, and where they want to hear and/orview it. Content that is available on a media server 3000 may beaccessed through a control point's 3004 content directory functionality.This directory may comprise a hierarchical organization of contentcategories in which a superhierarchy is “Music,” a sub-category withinMusic is “Artist,” a sub-category within Artist is “Album 1,” and soforth.

In embodiments, to cite one example among many potential embodiments, amedia server 3000, media renderer 3002, and control point 3004combination may be used to control a home audio visual system such asone including a compact disc player 3100, DVD player 3102 and aprojection screen 3104. In this home audio-visual example, a remotecontroller 3108 may be used to communicate with a plurality of controlpoints 3004, each of which is associated with a device within theaudio-visual system. For example, the remote controller 3108 maycommunicate with a control point 3004 associated with a compact discplayer 3100. The compact disc player 3100 may relay data to a mediaserver 3000 that, in turn, relays the data to the media renderer 3002and on to the control point 3004. Similarly, a DVD player 3102 andscreen 3104 may be controlled by a remote controller using a mediaserver 3000, media renderer 3002, and control point 3004 combination.

In embodiments, the portable node may be associated with a userinterface for controlling other aspects of the entertainment system. Forexample, a user may be able to control output channels, input channels,volume, pitch, balance, treble, bass, brightness, sharpness, HDTVfunctions and the like. A portable node with a user interface may beadapted as a controller/receiver for other devices, sensors and the likein the network.

A Subscriber Identity/Information Module (SIM) may uniquely identify aconnected mobile device and permit a mobile communication device tointerface with a mesh network. A SIM card may also provide configurablestorage for additional information related to a subscriber. As anexample, a SIM card may provide storage for subscriber personalinformation such as address books, preferences, telephone numbers,network passwords, and such other information that may be beneficial oruseful for a mobile user for accessing a wireless network.

Additionally, the SIM may facilitate accessing a mobile network. In anexample, the SIM may contain unique information that a GSM mobile devicenetwork may detect when the SIM is installed in a GSM compatible phoneand operated in a GSM network coverage area. Therefore when a mobilecommunication device, such as a mobile phone, is operating with a SIM inthe range of a wireless network, such as a wireless mesh network, themobile device may be detected by the network. In this way a SIM mayfacilitate making a mobile or portable device discoverable by a meshnetwork. Additionally, subscriber and/or network node identificationinformation on the SIM may be used in an authentication process prior toallowing the mobile phone to join the wireless mesh network.

In embodiments, a mobile communication device equipped with a SIM cardmay facilitate a user of the mobile device gaining authorized access toa mesh network and further access facilities on the mesh network. Forexample, an authenticated user of a mobile device on a mesh network maydownload to the configurable memory of the SIM a list of movies storedon a digital video recorder connected to the network. The mobile devicemay then use the downloaded list along with display format informationstored in the SIM to display the list in a user interface on the mobiledevice display. In another example, the user may upload digital contentsuch as photos or a video on the mobile device (e.g. a camera phone withvideo capability) to a home entertainment system for presentation to auser viewing the display of the home entertainment system. Such anexample may be used by an international traveler wishing to show imagesfrom their travels, or an Emergency Medical Technician providing imagesof an emergency patient in the field to an emergency room doctor.

Because a SIM may provide both access to a wireless network and mayprovide authentication for access to a mesh network, a SIM based mobiledevice, such as a cell phone, may be used to access the facilities of amesh network from a location that may be far outside the range of nodeson the wireless mesh network by accessing the mesh network through aportal from the mesh network to the cell phone network.

A portable or mobile node may be discoverable through informationcontained in the SIM, as other nodes are discoverable. For example, theportable node may be located by other nodes sending ‘find’ requests tothe portable node. Once the portable node configured with a SIM cardreceives a find request, it may respond and a communication link thathand-offs to other nodes in the network may then be completed. In otherembodiments, the SIM card may include configured storage informationthat directs the mobile device or portable node to send ‘find’identifiers periodically. For example, the mobile device may send abroadcast type data packet such that the nearby nodes that receive thedata may identify that they can communicate with the SIM based mobiledevice.

An aspect of the present invention relates to streaming data (e.g.entertainment data) through the mesh network. Streaming data may beadapted such that control frames can be transmitted over the meshnetwork while streaming data is transmitted. In embodiments, a softwarecomponent supporting streaming data may include a minimum delay of 35 msafter each frame carrying streaming data for example.

In embodiments, streaming data is preferably performed at a hightransmission rate (e.g. a 40 kbps transmission rate). A controllerstreaming the data may determine and select the optimal speed,preferably high speed (e.g. 40 kbps, or the highest speed available),for the stream transmission. Depending on the network topology, a slavemay not check communication speed of routed streaming data, andtherefore the controller may preferably select a low speed (for example9.6 kbps) for a routed data stream. In embodiments, a master controllerand/or the nodes in the mesh network that are handling the streaminginformation may select the highest speed path available for transmissionof the streaming data. For example, the streaming data may reach a nodeand the node may have the ability to pass the information to anyone of aplurality of nodes because the plurality is in range. The node maydetermine that one of the plurality is a high speed node and select thatnode for receiving the next data transmission. Once a high speed pathfrom source to ultimate receiver is determined, the routing informationfor the high speed path may be saved and used for later transmissionsrequiring high speed transmissions.

In embodiments, a number of methods and systems may be used for largedata file transmission. For example, large data files, such as textfiles, audio files, video files, and like, may be transferred in asingle block of data for an end-processing element to utilize when atransfer is complete. A large file may also be transferred in such a waythat the end-processing element buffers the incoming data, and after ashort delay, begins to utilize the data before the transfer is complete.A large data file may also be transferred in such a way that the data issent to the user in real-time, or near real-time.

Transferring a large data file, which may not be used immediately by theend-processing element, may be transferred as a single block of data. Anexample of this may be a television guide that is distributed toend-processing elements once a day for subsequent use. The lack ofimmediacy of this task may allow the sending unit to schedule thetransfer when bandwidth is available, transfer the data with or withoutdata compression, and data may only need to be stored, reducingprocessing requirements. This method of transferring a large data filemay be the least burdensome for the processing elements, but may not bethe best choice for large data files that may require immediate action,such as real-time audio and video files.

In embodiments, a large data file may be transferred for immediate usebased at least in part on buffering the data at the receiving end of thetransfer. This method is often referred to as progressive downloading orpseudo-streaming, and may not be fundamentally different from othermethods for transferring data for subsequent use. As a result, the samedata transfer protocols that the sending processing element uses forsmall data transfers may be utilized for progressive downloading. Thedata file may also be retained after transfer to the end-processingelement. One addition to the end-processing element, in order to aid inthe immediate use of the data by the user, is the addition of adata-buffering layer between the input from the source and the output tothe user. As long as the available bandwidth during data transferbetween processing elements is not less than the required data rate tothe user, the user may not be aware that the data transfer is stillongoing while the initial data is being used. When available bandwidthduring transfer is predicted to be less than that of the user, datacompression may be employed to reduce the throughput requirement. Datacompression rates may vary from low, for lossless data compressionschemes, through high, for lossy data compression schemes. In general,the receiving data buffer may also be expanded as an alternative to theneed for lossy data compression. This method generally maintains a highquality of file transfer, while allowing the user to begin using a fileprior to it's completed download.

Another method for transferring a large data file for immediate use mayinvolve the real-time transfer of data between the source and the user.This method is often referred to as streaming data. The process oftransferring data in real-time may require unique data transferprotocols from those used in non-real-time file transfers. Datatransferred in real-time may have to conform to predetermined datatransfer rates. Audio and video are both examples where the real-timedata rates are predetermined. In addition, when these predetermined datarates cannot be met by the source, data may have to be sacrificed inorder to maintain the real-time data steam rate. For example, lossy datacompression rates may have to be varied as bandwidth in the transfermedium becomes reduced. The increased data compression rates may reducethe quality of the real-time data, such as reduced quality audio or andincreased graininess of a video file output. Another example may be thedropping of short portions of an audio stream, the reduction of the sizeof a video output, or the momentary freezing of a web-cast. These issueswith streaming may be offset by the advantages of being able to skiparound in a video file without waiting for a download to complete, orhaving the ability to monitor a scene real-time. In addition, since thedata rates are known, being either predetermined or throughcommunication between the send and receive processing elements, thesending processor element may be able to more effectively utilizeavailable bandwidth. The end-processor element may also have no need tostore the data it is receiving, and so memory storage may be reduced.This method is generally utilized when real-time data is a higherpriority than the quality of the data transferred.

RF transceiver 802 benefits with improved sensitivity by employing ademodulator correlation function. The demodulator detects the frequencyof the FSK input signal by counting clock pulses between zero-crosses.In order to separate the two input frequencies an average filter is runon the input signal. The DC is subtracted from the input signal and theresult is sampled into a delay chain of registers. The demodulator thencorrelates this signal history to the pattern of the knownNRZ/Manchester symbols. For NRZ the correlation value is computed as thesum of the sampled input signal over one NRZ bit period. For Manchesterthe correlation value is computed at the sum of the first halfManchester bit period minus the sum of the second half bit period. Thebit slicing is performed by checking the sign of the correlationfunction at the rising edge of the recovered clock. This results inimproved sensitivity.

In embodiments, a demodulator, such as that illustrated in FIG. 29, maybe designed so that it can detect Manchester (MCH) code at 9.6 kbit/s2902 and NRZ code at 40 kbit/s 2904 and 100 kbps 2908. It may be set inthree different modes: (i) to detect and receive only MCH data (9.6kbit/s) 2902; (ii) to detect and receive only NRZ data (40 kbit/s) 2904;or to detect and receive only NRZ data (100 kbit/s) 2908.

In embodiments, when a demodulator is in an auto mode, both MCH and NRZdata may be detected. Once a frame is detected as either MCH or NRZ, thedemodulator may switch to this mode and start receiving data in an automode. In the auto mode the demodulator must listen for Manchester (MCH)code at 9.6 kbit/s 2902 and NRZ code at 40 kbit/s 2904 and 100 kbps2908. In order to do this the demodulator may contain three detectors,one for MCH and two for NRZ. However some part of the demodulator may becommon for both detectors, such as the IF detection 2900, filtering2900, and the control of the demodulator 2910.

RF communication error detection may be improved by the use of CRC 16,or other similar robust error detection techniques, on elements of thecommunication signal including Z-wave frames.

Referring further to FIG. 9, transceiver 802 may transmit using amodulation frequency that is asymmetrical to a reference carrier/localoscillator frequency, resulting in a transmit frequency that is notsupported by the reference frequency synthesizer. By supportingasymmetric radio frequency signal modulation, transceiver 802 has theability to transmit on a frequency not supported by the frequencysynthesizer.

Referring to FIG. 9A, a waveform diagram representing selection ofasymmetric modulation, if offset control 910 is set at its centerfrequency 920 during settling of PLL 930, modulation 940 will go to bothsides of PLL 930 frequency. As an example, this may correspond to binaryFSK with a carrier frequency at an integer multiple of 200 kHz.

Referring to FIG. 9B, if offset control 910 is set at the zero symbolsetting 950 during settling of PLL 930 then modulation 940 will only goto an upper side of PLL 930 frequency. As an example, this maycorrespond to binary FSK with a carrier frequency at half the modulationseparation above an integer multiple of 200 kHz or N×200 kHz+20 kHz toN×200 kHz+25 kHz. Benefits of asymmetric modulation include the abilityto transmit on a frequency not supported by the frequency synthesizer.

RF transceiver 802 may include a Phase Lock Loop (PLL) which may besynchronized while the system is powering up. Such synchronization mayreduce locking time, afford faster RF turn-on, and lower powerconsumption

PLL divider synchronization at start-up to reduces locking time. The VCOfrequency is divided by a circuit denoted as the PLL divider, into asignal that matches a well defined reference signal. The referencesignal is generated from the system clock and can be optionally 100 kHzor 200 kHz. During calibration, the center frequency of a VoltageControlled Oscillator is adjusted so that the divided frequency aftercalibration is very close to the reference frequency. After calibrationa PLL fine-tunes the divided VCO signal so that it locks completely ontothe reference signal.

In order to minimize VCO lock settling time, the PLL and the referencesignal are disabled and then released simultaneously after calibration.The result of simultaneous release is a synchronization action whereboth signals start at the beginning of their high period. Thesynchronization between the signals minimizes the PLL settling time,resulting in faster turn-on of radio, and lower power consumption.

RF transceiver 802 includes an RF transmitter including a transmitterdigital to analog converter which delivers the benefit of reduced cost.The transmitter chain contains a D/A converter which has two functions.The first is to convert the digital encoded bit symbols to analogsignals, and the second is to set the transmission power of thetransmitted RF signal, since the D/A converter is followed by a fixedgain PA amplifier. The D/A converter is a digital symbol to sine-voltageconverter. Each output voltage of the D/A is a discrete step on asine-curve which is selected by the digital value on the input. Athermometer coded signal is applied, and each value of the input signalselects a step on the sine wave. Counting from 0 to 31 and back again istherefore generating a full sine-period. The advantage of havingsine-sized D/A steps is, that a low number of control-bits can generatea high resolution sine-wave. Further more, the amplitude of thesine-wave is controllable, which means, that the transmission strengthof the RF signal is set in the D/A.

Referring to FIG. 9C, VCO frequency calibration ensures that an analoguecontrol voltage 9110 input to VCO 9120 is preferably within a narrowrange and compensates for variation of on-chip capacitance which affectsVCO 9120. During calibration, PLL loop filter 9130 is opened and Calblock 9140 sets VCO control voltage 9110 to a predetermined value. Acalibration control block 9150 may adjust the frequency of VCO 9120 bychanging capacitance values internal to VCO 9120.

Referring further to FIG. 9D, for various cal control 9150 settings ofVCO 9120 capacitors, output frequency of VCO 9120 is measured by using alock detector 9160. After resetting of the different dividers tosynchronize all blocks, lock detector 9160 may compare a subdividedversion 9122 of VCO 9120 output frequency to a reference clock 9180. Byusing a successive approximation approach the correct calibrationsetting can be determined in very few reference clock 9180 cycles. FREQHigh and FREQ Low bits generated by lock detector 9160 are used incalibration control circuit 9150 to indicate if VCO 9120 frequency istoo high or too low.

To ensure the PLL locks precisely onto a predetermined frequency,reference clock 9180 and subdivided VCO output 9122 are preferablysynchronously released. In embodiments, reset circuit 9190 mayautomatically issue synchronous reset signal 9192 upon receiving asignal from calibration control 9150. Alternatively, a softwareaccessible control register can be used to signal reset circuit 9190 toissue synchronous reset signal 9192.

FIG. 9D illustrates a calibration sequence wherein 4 bits of calibrationcontrol information 9210 is passed from calibration control circuit 9150to VCO 9120 (as shown in FIG. 9C). For each calibration information 9210setting, freq high signal 9220 may respond on a rising edge of referenceclock 9180, further enabling a change in calibration information 9210setting. This sequence repeats until PLL frequency 9230 is substantiallyclose to a predetermined value.

Referring to FIG. 9C and FIG. 9E, in receive mode during periods when nopreamble or SOF has been detected and no data is currently beingreceived, calibration control 9150 may adjust calibration settingwhenever VCO control voltage 9110 has changed significantly. Thisfunction is done by sense block 9105 by comparing VCO control voltage9110 with an upper limit 9310, and a lower limit 9320. As illustrated inthe diagram in FIG. 9E, VCO control voltage 9110 may be monitoredcontinuously such that when it falls outside sense block 9105 limits,calibration control 9150 adjusts calibration information setting 9210.In embodiments, a sudden change in calibration control 9150 output willresult in PLL 9230 loosing lock, therefore calibration control 9150 maybe disabled until lock detector 9160 indicates that PLL 9230 has settledagain.

Additionally, voltage controlled oscillator (VCO) calibration may useportions of the PLL, thereby reducing hardware resources and cost.Additionally cost is reduced by IF calibration. In order to counteractthe natural variation in resistors and capacitors, the IF filters of theZW0201 has programmable resistors, which are set during a calibrationprocess. This calibration process is able to reduce the variation of theIF filter center frequency, and this helps relax the requirements to thesystem clock. The calibration is performed using the components of theIF filter. The procedure is like this: One capacitor is discharged andanother is charged. The voltages across the capacitors are compared, andwhen they cross each other, the charge/discharge time is recorded (asbeing the time from start of the process until the voltages cross eachother). The two capacitors are reset, the programmable resistors of theIF filter is changed, and another charge/discharge sequence is done.Four charge/discharge periods are performed, and resistors are changedduring each period, which results in a resistor setting that has aoptimal charge/discharge period.

The single chip embodiment of FIG. 8 contains an embedded MCU 830. Oneexample of a preferred MCU is embedded 8051 MCU core (Inventra M8051Warp) including two standard 8051 timer/counters 804. MCU830 may becompatible with industry standard 803 x/805 x MCUs. The single chipsolution may allow for optimisation of MCU 830. MCU 830 of theembodiment of FIG. 8 completes one instruction cycle per two clockcycles as opposed to a standard 8051 with 12 clock cycles perinstruction cycle. This makes MCU 830 six times faster than the standard8051.

Referring to FIG. 10, a timing diagram of a pulse width modulated output(PWM), general purpose timer 804 is a timer that may be polled orprogrammed to generate interrupts. Timer 804 may be an auto-reloadcounter with a fixed clock divider ratio. The timer of the single chipsolution of FIG. 8 uses a 16-bit timer that may be an auto-reloadcounter with a fixed clock divider ratio of either 4 or 512. Timer 804may also be set in Pulse Width Modulation (PWM) mode. The PWM may becontrolled by setting the total period and the total high period. Thisembodiment utilizes an 8-bit register to set the total period and an8-bit register to set the high period, therefore timer 804 counts usinga fixed clock divider ratio of either 4 or 512.

Wake up timer 838 may be an ultra low power timer that may be enabled ina sleep mode or power down mode to wake up MCU 830 after a programmabletime period. The sleep period may be configurable in number of seconds,such as in a range of 1 to 256 seconds. Wake up timer 838 is based on aninternal oscillator that may be automatically calibrated against thesystem clock. IN the preferred embodiment of FIG. 10, wake up timer 838may automatically calibrate during power-down mode, resulting in aneasier to use system that automatically calibrates under the sameconditions as when operating.

Special function registers 840 may contain registers that are used tocontrol MCU 830 operating mode, and the operating mode of built-inperipherals.

Various memory technologies may be used for MCU program store,application store, and for internal/external data storage. In thepreferred embodiment of FIG. 8, two types of memory are used.

A 32 kbytes of flash memory 828 is MCU 830 program memory containingmesh network 100 API and customer application software. MCU 830 also hasthe ability to read, write and erase the flash memory 828. Flash memory828 has a built-in read back protection in order to prevent reverseengineering or design theft. Clearing a dedicated lock bit in flashmemory 828 activates the read back protection. As long as the lock bitis cleared it is not possible to read from the flash memory 828externally. Other lock bits may protect parts of the flash againstwriting. The lock bits may only be unlocked by erasing the entire flashmemory.

256 bytes of Internal Random Access Memory (IRAM) 832 may be used by MCU830 for 8051 internal data memory, and may also be accessed throughdirect instructions from MCU 830.

2 kbytes of External Random Access Memory (XRAM) 832 may be used by MCU830 as 8051 external data memory. The single chip implementation of FIG.8 may contain an interrupt controller 818, supporting 10 interruptsources including two external interrupt sources on through GeneralPurpose I/O's. Some of the interrupt sources may be reserved by the meshnetwork API. The Interrupt Controller controls the interrupt priorityassignment. The priority may be fixed by the mesh network protocol. Theexternal interrupt may also be enabled to wake up the chip from Sleepmode. The single chip implementation of FIG. 8 may further contain aTriac Controller 820 for power regulating applications. Triac Controller820 may be compatible with 50-60 Hz external alternating current power.Using an external Triac and a few extra external passive components acomplete phase control circuit may be designed. Triac controller 820 maybe implemented in a separate circuit within the single chip in order tokeep timing and operation independent of software and to minimise MCU830 workload.

In embodiments, a Triac controller within an integrated circuit meshnetwork node may be used to deliver power to a load, wherein timing ofthe power delivery is based at least in part on a zero crossing point ofan AC power signal. The load may be a resistive load or a non-resistiveload (e.g., an inductive load). The power delivery may be based at leastin part on a fire angle. The power delivery may be initiated incoordination with a fire angle. The power delivery may be terminated incoordination with the zero crossing point. In embodiments, the Triaccontroller may be associated with a noise mask adapted to reduce falseindications of zero crossing.

The mesh network node 100 may contain an analog-to-digital converter(ADC) 822 with a resolution that may be set to 8-bit or 12-bit. An 8-bitconversion takes less than half the time of a 12-bit conversion. ADC 822may be rail-to-rail and programmed to refer to various internal orexternal voltage references. The ADC block may include abattery-monitoring mode. ADC 822 may support both single and continuousmulti conversion mode. ADC 822 may have a built-in comparator forgenerating interrupts when a threshold set by software is exceeded. Thethreshold may be either a low threshold or a high threshold. It ispossible to shut down ADC 822 for reducing power consumption. ADC 822also includes self test capability which may reduce test related costs.

The 8-bit part of the ADC is tested for missing codes, mismatch andmissing connections in a simple and fast way. The precision of the testis better than ½ LSB. The 8 bit part of the LSB is made of 9 capacitors,8 capacitors having an individual size ratio which is binary and 1capacitor having the unit size. The largest of the 8 capacitors is 2̂7units large, called C0, the next is 2̂6, called C1, down to C7, which is2̂0 units large. The 9.th capacitor, having the unit size 1, is called Cs(for stationary). The capacitors presence and size ratio is tested bytesting C0 against C1+C2+ . . . C7+Cs and adding an extra test-capacitorhaving the size of ½ unit. Since C0 is =C1+C2+ . . . C7+Cs, adding theextra ½ lsb capacitor (called Cc) ensures that the term. C1+C2+ . . .C7+Cs+Cc is now for sure larger than C0. If any capacitor units missesin any of the 9 capacitors (C0 . . . C7+Cs), the test will fail. Next,C1 is tested against C2+ . . . C7+Cs, etc. The test is very fast toperform and does not require any high precision external stimuli orconventional ADC conversion cycles. If this test should be performed ina normal fashion, 256 ADC conversions with an input voltage ranging from0V to Vdd would have to be performed. With the new approach, this testtime is reduced to app. the time it takes to perform one ADC conversion.

A software programmable interface (SPI) 824 may be included in theimplementation. Two examples of how SPI 824 may be used are: 1) toprovide external access to the flash memory 828 and 2) to allow meshnetwork node 100 to communicate with an external memory. The SPI may actas a master or slave when interfacing to memory. For example, networknode 100 acts as a master when accessing external Electrically ErasableRead Only Memory (EEPROM) and as a slave when accessing the flash memory828. External flash memory may also be accessible by MCU 830.

The mesh network node embodiment of FIG. 8 may contain a UART 814 andmay operate independent of MCU 830. UART 814 may support full duplex andmay operate with the following three baud rates: 9.6 kbaud, 38.4 kbaud,or 115.2 kbaud.

Power Control Block 838 controls node 100's different power savingmodes. For example two power saving modes are: Normal Mode and SleepMode/Power Down Mode. In Normal Mode MCU 830 is running and the RFcircuits and ADC 822 may be powered up or down. Sleep Mode/Power DownMode may be the lowest power mode, with everything shut down except theRAM's brown-out detection and low power timer. In addition ADC 822 maybe powered up or down. In Sleep mode it is possible to wake MCU 830 upusing an external interrupt source. The source may be active low oractive high. MCU 830 may also be woken by the wake up timer 838, areset, or by power cycling.

It is also possible to power down MCU 830 while keeping RF transceiver802 operating, by automatically stopping MCU 830 before powering up RFtransceiver 802. Additionally, it is possible to restart MCU 830 whentransmission has completed and RF transmitter 802 has been powered down.This sequence of powering up and down these elements reduces powerconsumption and cuts peak current demand.

Two examples of how this may be executed is: automatically stopping theMCU before powering up the radio and transmitting, and restarting itwhen transmission has completed and the radio powered down; andautomatically stopping the MCU before powering up the radio forreception and automatically powering up the MCU when a signal isreceived

Depending on information frames contained within a signal received by RFtransceiver 802, MCU 830 can be automatically powered up. A framehandler coupled to RF transceiver 802 automatically detects Z-waveframes and can automatically generate a signal to power-up MCU 830 orgenerate an interrupt to MCU 830 if it is already powered-up. Thebenefit of the frame handler functionality is reduced operating load onMCU 830, lowering memory requirements, and reducing power consumption.

This embodiment also has general purpose I/O interfaces 808. Forexample, the ZW0201 has 10 configurable General Purpose I/O (GPIO) pinswith optional weak internal pull-up. The GPIO pins may be organized astwo ports. The GPIO pins may have dual or even triple functionality,user programmable from MCU and some special hardware functions (forinstance SPI 824, ADC 822, UART 814, TRIAC controller 820, etc.). Inthis implementation four of the GPIO pins may be either analogue (forADC) or configured for digital interfacing as an input, or output. ResetI/O may also be available. Two examples of reset I/O are 1) Externalreset and 2) Enable programming mode. For example, when the reset pin ispulled low a master reset is generated. If the reset is held low for anextended period then the chip accepts programming commands on SPI 824.The chip may not go into actual programming mode until an SPI 824Programming Enable command is received. As an example five dedicatedanalogue pins are used for RF interface 802 and crystal connections 810.GPIO pins may be set as inputs during reset. This pin configuration maybe maintained after the reset is released until the software changes thesetting.

By using one or more of the invention interface circuits, anRC-oscillator may be used as a temperature sensor, lowering cost byreusing existing interface circuits for the additional function ofsensing temperature. The Wake-up timer internal ring oscillator isdesigned in a way so the calibration value has a near linear temperaturedependency. The calibration depends on temperature, supply voltage andprocess variation. Fortunately the supply voltage variation can be takeinto account by using the built in battery monitoring circuit. Theimpact of process variation is mostly on the offset value. Consequentlyif the calibration value is known at a given temperature then thetemperature can be estimated at another temperature. This results in thebenefit of low cost from reuse of existing circuit as temperaturesensor.

The single chip 100 implementation may contain a number of externalinterfaces including general I/O 808, clock signals 810, resets 812,transceiver I/O 802, UART 814, interrupts 818, Triac control 820, ADC822, SPI 824, and external memory. FIG. 11 shows the I/O for a typicalapplication circuit.

Clock signals 810 may require external interfaces. For example FIG. 12shows external crystal 1200 connections. Node 100 includes an on-chipcrystal oscillator making it possible to drive a crystal directly andcan operate with either a 32 MHz or a 16 MHz crystal. An external loadcapacitor 1202 may be required on each terminal of the crystal. Theloading capacitor values may depend on the total load capacitancespecified for the crystal.

FIG. 13 shows a simplified block diagram of an internal reset circuit812. For example all pats of node 100 are reset when one or more of thefollowing conditions are true: 1) Reset 1300 is low, 2) WhenPOR/brown-out detection circuit detects low supply voltage, 3) WhenWATCHDOG 1302 times out. The reset may be an asynchronous input withinternal pull-up, schmitt trigger, and glitch protection. The signal maybe synchronized internally so that the reset may be asserted anddeasserted asynchronously. The POR circuit may also contain a low passfilter 1304 for glitch protection and hysteresis 1308 for noise andtransient stability. In Sleep mode the POR may go into a low power modethat protects the circuit against brown-out while keeping the powerconsumption at an absolute minimum. During master reset all GPIO 808pins may be configured as inputs and the RF Transceiver 802 may be setin power down condition.

FIG. 14 shows the RF connections in a typical application. RFtransceiver 802 may require very few external passive components 1400,1402 for input and output matching. IN this embodiment an internal T/Rswitch circuit 1404 makes it possible to match the receive (RX) andtransmit (TX) independently. L1/C1 1400 is used for matching thetransmitter output to 50Ω L2 1402 may be used for matching the receiverinput to 50Ω. The values of the matching components may depend on theactual PCB layout. Moreover the matching components should be placed asclose as possible with efficient grounding in order to achieve bestperformance. Additional external filter components may be added in orderto filter the RF harmonics (if necessary) and improve the blockingperformance.

UART 814 interfaces with external components. For example UART 814interfaces with a data rate of 9.6 kbaud, 38.4 kbaud, or 115.2 kbaud,with 8-bit words, one start bit, one stop bit and no parity. FIG. 15shows a typical RS232 UART application circuit. FIG. 16 gives a waveformof a serial byte. UART 814 shifts data in and out in the followingorder: start bit 1600, data bits 1602 (LSB first) and stop bit 1604. Fornoise rejection, the serial port may establish the content of eachreceived bit by a majority voting on the sampled input. This isespecially true for the start bit. If the falling edge on R×D is notverified by the majority voting over the start bit then the serial portstops reception and waits for another falling edge on R×D. After ⅔ ofthe stop bit time, the serial port waits for another high-to-lowtransition (start bit) on the R×D pin.

Single chip embodiment of network node 100 supports external interrupts818 to MCU 830 as shown in FIG. 17. For example, Interrupts 1700 may beprogrammed to be either level-triggered (high/low) or edge-triggered(rising/falling). Also, interrupt(s) to Power Management 838 may enablewake up from sleep mode. Interrupts may be used to wake up the chip fromsleep mode. The interrupts to the Power Management 838 may belevel-triggered (high/low). When the chip wakes up from Sleep mode theclock oscillator may start up before program execution starts.

This implementation may have a Triac Controller 820 which uses phasecontrol for power regulation of resistive loads 1800 and to some degreenon-resistive loads. FIG. 18 shows a simplified application circuit. Thephase control method may conduct power during a specific time period ineach half of the AC power cycle. FIG. 19 shows typical Triac waveforms.A Triac is commonly used to switch on and off the power to the load inthe AC power system application. A gate voltage 1900 may be required toturn on the Triac (fire pulse). Once “on”, the Triac may stay “on” untilthe AC sine wave reaches zero 1902 current regardless of the gatevoltage. The power regulation is performed by controlling the fire angle(turn on start time). The Triac may deliver the power to the load afterthe fire angle and turn off at the zero-crossing point. The fire pulsemust be of a certain duration in order to 1) provide sufficient chargefor the Triac to turn on and 2) ensure that is does not subsequentlyswitch off due to potential noise. The duration of the fire pulse may beprogrammed in SW. The zero cross detection may be disturbed by noise2000 on the AC line. In case this noise is strong enough it could worstcase cause additional triggering 2002 on the ZEROX as shown in FIG. 20.In order to avoid these extra zero crossing triggers a noise mask 2100has been implemented in the Triac Controller. The mask masks out zerocrossings from the true zero cross until a period before the next truezero cross, as shown in FIG. 21. The zero cross detector may either beprogrammed to use both the rising edge and the falling edge of the zerocross signal 1900 (like the ZEROX signal in FIG. 19) or it may beprogrammed to only use the rising edge of the zero cross signal 2200(like the ZEROX signal in FIG. 22). The Triac Controller may beprogrammed to generate an interrupt request to the MCU whenever itdetects a zero cross. When detecting zero crosses on both rising andfalling edges then the detection moments may be offset 2300 due to thethreshold level of the ZEROX input, as shown in FIG. 23. Because of thisoffset the Triac fire pulse may not be fired at the same distance fromthe beginning of the positive period and from the beginning of thenegative period. It means that the AC load, which the Triac controls,may have a DC voltage different from 0V. To make this DC voltagenegligible, the Triac Controller may be programmed with a variablecorrection 2400 period to correct for the offset, as shown in FIG. 24.

In order to control a Triac, two signals are important. The ZEROXsignal, which reflects the zero crossing of the mains signal, and theTRIAC signal, which is used to fire the Triac. The ZEROX signal is usedto generate a fire pulse (TRIAC signal) for every half period, that is,both the rising edge and the falling edge are used as time base forgenerating the fire pulse. The zero-cross detection logic isn't togglingexactly on the zero cross because of the threshold level of the inputbuffer of the ZEROX pin. Therefore the fire pulse in the “negative” halfperiod will be slightly earlier than the fire pulse in the “positive”half period. This difference generates an unwanted DC current in theconnected appliance. To correct for this difference; a programmingregister, TRICOR, can be used to skew the time for the generation of thefire pulse in the negative half period, thus removing the difference andavoid DC in the controlled load. A benefit of this Triac controlfunctionality is avoiding DC in the controlled load (specifically aproblem for inductive loads).

External interfaces are required for the ADC 822. ADC 822 may be aversatile rail-to-rail converter, which may operate in high-resolution12-bit mode or a fast 8-bit mode. The ADC may be connected to theexternal circuit using GPIO 808 pins. The ADC may sample an analoguesignal on any of the pins. The ADC is able to perform single conversionor continuous multi conversion. The ADC block may be programmed togenerate an interrupt to the 8051W when a certain high or low thresholdis exceeded. FIG. 25 gives an overview of the internal ADC block. TheADC may also be used for monitoring the supply level. In this set-up theInternal Reference 2502 is measured with reference to the supply level.The ADC input signal may be loaded by an internal sampling capacitor. In8-bit mode the sampling time may be configured to fit the sourceimpedance and frequency contents of the input signal. Alternatively aninternal buffer may be switched in between the external source and theADC to reduce capacitive loading of the input.

SPI 824 may be used for synchronous data transfer between the singlechip 100 device and an external memory, used by some node types, orbetween a programming unit and the device. The SPI may not be availableto the external application. Mater mode 2600 is activated wheninterfacing to an external EEPROM and slave 2602 during programmingmode. The programming mode may be enabled by setting Reset low for anextended period. The SCK may be the clock output in master mode and isthe clock input in slave mode. During data transmission the SCK mayclock the data from a slave register into a master register. At the sametime data may be clocked in the opposite direction from master to theslave connection. Consequently the two registers 2604 may be consideredas one distributed circular shift register as illustrated in FIG. 26.After 8 clock cycles the two registers will have swapped contents. FIG.27 shows a typical interface application to an EEPROM.

An embodiment may contain a function for programming external memory,such as external Flash memory. In flash programming mode an externalmaster may control the SPI bus causing node 100 to act as slave. Inprogramming mode the flash may be erased, read, and/or written. Moreoverit is possible to read a signature byte identifying the chip,enable/disable read/write protection, and/or read/write the Home ID.Flash programming mode may be entered by setting and keeping the Resetpin low. When the Reset has been held low for two XTAL periods then theSPI may accept a Programming Enable command. The chip may not enterprogramming mode until the two first bytes of the Programming Enable hasbeen accepted. After the chip has entered programming mode the devicemay stay in programming mode as long as the Reset pin is held. When theReset pin is set high the chip may generate an internal master resetpulse and normal program execution may start up. The watchdog functionmay be disabled as long as the chip is in programming mode and all otherGPIO's 808 than the SPI 824 interface may be tri-stated. FIG. 28 gives asimplified block diagram of a typical interface to programmingequipment.

Referring to FIG. 32, the present invention may include a method andsystem for silently acknowledging a successful transmission of a singlecase frame from a first node to a second node. For example, a singlecast frame 3208 may be sent from a first node 3200 to a third node 3204by using a second node 3202 as an intermediate relay between the first3200 and third nodes 3204. As the second node 3202 sends the single castframe 3209 that it received from the first node 3200 onto the third node3204, the first node 3200 may be able to detect the single cast frame3209 sent from the second node 3202 to the third node 3204 and interpretthis single cast frame 3209 as an acknowledgement of success in sendingthe single cast frame 3208 from the first node 3200 to the second node3202. Third node 3204 may send a routed acknowledgement frame 3210 tonode two 3202 indicating that it received the single cast frame 3209from node two 3202. The third node 3204 may be able to detect the routedacknowledgement frame 3211 sent from the second node 3202 to the firstnode 3200 and interpret this routed acknowledgement frame 3211 as anacknowledgement of success in sending the routed acknowledgement frame3210 from the third node 3204 to the second node 3202. The first node3200 may then send an acknowledgement 3212 to node two 3202 that itreceived the routed acknowledgement frame 3211 from node two 3202. Thisprocess may be repeated throughout a single cast frame transmissionsequence, with subsequent nodes (e.g. the fourth or sixtieth node in atransmission sequence, etc.) wherein a sending node detects atransmission from a receiving node to a third node, and interprets thisas acknowledgement that the receiving node successfully received atransmission from the sending node

In embodiments, this silent acknowledgement routing schema may beimplemented through an ASIC or any other consolidated processor platformdescribed herein and or illustrated in the included figures.

In embodiments, a second single cast frame may be sent from the secondnode to a third node in a mesh network, and detection of the secondsingle cast frame by the first node interpreted as an acknowledgement ofsuccess in sending the first single cast frame from the first node tothe second node. A single cast frame may be a routed single cast frame.It may be routed based at least in part on a routing table. A singlecast frame may be related to a metadata, a command, or some other formof data. A command may relate to including and or excluding a node in amesh network, to enabling a security functionality, to a communicationspeed, to a communication channel, to a communication channelavailability, to a network security level, to a network topology, to anetwork routing strategy, or some other command type.

In embodiments, a network mandated speed may be 9.6 kbps, 40 kbps, 100kbps, or some other communication speed.

In embodiments, a communication channel availability may be associatedwith a single channel or a plurality of channels.

In embodiments, a network security level may be high, medium, low, orsome other network security level.

Still referring to FIG. 32, a single cast frame may be routed over amesh network topology that is an automation system network forcontrolling a device. A device may be a plurality of devices. Inembodiments, the mesh network topology may be implemented within a home.A home mesh network topology may be related to an audiovisual system,such as an audiovisual system including an entertainment device. Anentertainment device may be a television, a signal conversion device, aDVR, a networked device, a UPnP networked device, a satellite receiver,a cable converter, a VCR, a digital video disc player, a videoaccessory, an audio amplifier, an audio tuner, an audio amplifier-tunercombination, a CD player, a DVD player, a high definition DVD player, anaudio cassette player, a digital audio tape player, an audio equipment,an equalizer, a phonograph player, a video component, a streaming mediaplayer, an mp3 player, an audio file player, and audio component, anaudio-visual component, or some other entertainment device.

In embodiments, the mesh network topology may be related to a securitysystem. A security system may include an alarm, a lock, a sensor, adetector (such as a motion detector, and the like), or some othersecurity system component.

In embodiments, the mesh network may be a wireless mesh network.

In embodiments, a node within the mesh network may be a multi-speednode.

FIG. 33A illustrates a simplified embodiment for dynamically enablingchannel selection within a mesh network containing three channels. Anode may begin a scan one 3308 on channel one 3300 and remain on thechannel for a predefined duration. If the node does not detect a signal,the node may switch to channel two 3302 and begin scan two 3310. Ifduring scan two 3310 a signal is not detected, the node may switch tochannel three 3304 and begin scan three 3312. If no signal is detectedduring scan three 3312, the node may cycle back to channel one 3300 andbegin scan four 3314. If no signal is detected during scan four 3314,the node may switch to channel two 3302 and begin scan five 3318. Inthis simplified hypothetical example, a signal may be detected duringscan five 3318 on channel two 3302. As depicted in FIG. 33B, the signalthat is detected during scan five 3318 may be a preamble 3334 thatindicates to the node that a message is to follow and that the nodeshould remain on channel two 3302 beyond the predefined durationoriginally set for scan five 3318. Following receipt of the preamble orplurality of preambles, the node may receive message one 3330 overchannel two 3302. Following receipt of message one 3330, the node mayswitch to channel three 3304 and remain on the channel for thepredefined duration of scan six 3320. If no signal is received duringscan six 3320, the node may switch back to channel one 3300 and beginscan seven 3322. Scan seven may include a signal, such as a preamble orplurality of preambles, and remain on channel one 3300 beyond thepredefined duration in order to receive message two 3332. Followingreceipt of message two 3332, the node may continue switching channels inscan eight 3324, scan nine 3328, and so forth, remaining on a channelfor a predefined duration in order to detect a signal, and switchingchannels once the predefined duration has expired without a signaldetected.

In embodiments, the message received by a node may be a plurality ofmessages. The message may be a command. A command may relate toincluding and or excluding a node in a mesh network, to enabling asecurity functionality, to a communication speed, to a communicationchannel, to a communication channel availability, to a network securitylevel, to a network topology, to a network routing strategy, or someother command type.

In embodiments, the dynamic enablement of a secondary channel describedherein may be implemented through an ASIC or any other consolidatedprocessor platform described herein and or illustrated in the includedfigures.

In embodiments, a network mandated speed may be 9.6 kbps, 40 kbps, 100kbps, or some other communication speed.

In embodiments, a communication channel availability may be associatedwith a single channel or a plurality of channels.

In embodiments, a network security level may be high, medium, low, orsome other network security level.

In embodiments, the signal may be a predefined signal type.

In embodiments, the signal may be an implementation specific preamblesignal. The implementation specific preamble signal may be predefined.The implementation specific preamble signal may be dynamically defined.In embodiments, the implementation specific preamble signal may equal aspecific number of preamble symbol (a symbol consists of one or morebits). A preamble with less than the specific number of preamble signalsmay generate a command for a node to change to another channel. Apreamble with equal the specific number of preamble symbol may generatea command for a node to remain on the current channel. A preamble withgreater the specific number of preamble signals may generate a commandfor a node to remain on the current channel. The selection of the secondchannel may be based at least in part on a combination of receiving thesignal and a round robin algorithm, a combination of receiving thesignal and a predefined algorithm, a combination of receiving the signaland a locally based heuristic, or some other signal-rule combination.

In embodiments, the mesh network is a wireless mesh network.

In embodiments, the present invention may provide a method and systemfor using a first node to select a first channel in a mesh network;transmitting a frame over the first channel to a second node in the meshnetwork; and using the first node to select a second channel over whichto transmit the frame to the second node if failure of the transmissionover the first channel to the second node is detected by the first node.

While the invention has been disclosed in connection with the preferredembodiments shown and described in detail, each of the technologiesdescribed herein may be incorporated, associated with, combined, and thelike with each of the use scenarios described herein, and each of theapplications described herein, including market applications.

The elements depicted in flow charts and block diagrams throughout thefigures imply logical boundaries between the elements. However,according to software or hardware engineering practices, the depictedelements and the functions thereof may be implemented as parts of amonolithic software structure, as standalone software modules, or asmodules that employ external routines, code, services, and so forth, orany combination of these, and all such implementations are within thescope of the present disclosure. Thus, while the foregoing drawings anddescription set forth functional aspects of the disclosed systems, noparticular arrangement of software for implementing these functionalaspects should be inferred from these descriptions unless explicitlystated or otherwise clear from the context.

Similarly, it will be appreciated that the various steps identified anddescribed above may be varied, and that the order of steps may beadapted to particular applications of the techniques disclosed herein.All such variations and modifications are intended to fall within thescope of this disclosure. As such, the depiction and/or description ofan order for various steps should not be understood to require aparticular order of execution for those steps, unless required by aparticular application, or explicitly stated or otherwise clear from thecontext.

The methods or processes described above, and steps thereof, may berealized in hardware, software, or any combination of these suitable fora particular application. The hardware may include a general-purposecomputer and/or dedicated computing device. The processes may berealized in one or more microprocessors, microcontrollers, embeddedmicrocontrollers, programmable digital signal processors or otherprogrammable device, along with internal and/or external memory. Theprocesses may also, or instead, be embodied in an application specificintegrated circuit, a programmable gate array, programmable array logic,or any other device or combination of devices that may be configured toprocess electronic signals. It will further be appreciated that one ormore of the processes may be realized as computer executable codecreated using a structured programming language such as C, an objectoriented programming language such as C++, or any other high-level orlow-level programming language (including assembly languages, hardwaredescription languages, and database programming languages andtechnologies) that may be stored, compiled or interpreted to run on oneof the above devices, as well as heterogeneous combinations ofprocessors, processor architectures, or combinations of differenthardware and software.

Thus, in one aspect, each method described above and combinationsthereof may be embodied in computer executable code that, when executingon one or more computing devices, performs the steps thereof. In anotheraspect, the methods may be embodied in systems that perform the stepsthereof, and may be distributed across devices in a number of ways, orall of the functionality may be integrated into a dedicated, standalonedevice or other hardware. In another aspect, means for performing thesteps associated with the processes described above may include any ofthe hardware and/or software described above. All such permutations andcombinations are intended to fall within the scope of the presentdisclosure.

While the invention has been disclosed in connection with the preferredembodiments shown and described in detail, various modifications andimprovements thereon will become readily apparent to those skilled inthe art. Accordingly, the spirit and scope of the present invention isnot to be limited by the foregoing examples, but is to be understood inthe broadest sense allowable by law.

All documents referenced herein are hereby incorporated by reference.

1. A method comprising: transmitting a frame from a source node to anintermediate node; at the source node and during a time interval,failing to detect transmission of the frame by the intermediate node;and retransmitting the frame from the source node to the intermediatenode after expiration of the time interval.
 2. The method of claim 1,further comprising: at the source node and during the time interval,failing to receive a routed acknowledgement frame from the intermediatenode to the source node.
 3. The method of claim 1, wherein the timeinterval includes a randomly generated time interval.
 4. The method ofclaim 1, wherein transmitting includes unicast transmitting.
 5. Themethod of claim 1, wherein retransmitting includes unicastretransmitting.
 6. The method of claim 1, wherein each of the sourcenode and intermediate node includes a mesh network node in a wirelessmesh network, and wherein the transmitting and retransmitting occurwirelessly within the wireless mesh network.
 7. A method comprising:receiving a frame at a destination node from an intermediate node;transmitting a routed acknowledgement frame from the destination node tothe intermediate node; at the destination node and during a timeinterval, failing to detect transmission of the routed acknowledgementframe by the intermediate node; and retransmitting the routedacknowledgement frame from the destination node to the intermediate nodeafter expiration of the time interval.
 8. The method of claim 7, whereinthe time interval includes a randomly generated time interval.
 9. Themethod of claim 7, wherein transmitting includes unicast transmitting.10. The method of claim 7, wherein retransmitting includes unicastretransmitting.
 11. The method of claim 7, wherein each of thedestination node and the intermediate node includes a mesh network nodein a wireless mesh network, and wherein the transmitting,retransmitting, and receiving all occur wirelessly within the wirelessmesh network.
 12. A method comprising: transmitting a frame from a nodeto an intermediate node; at the node and during a first time interval,failing to detect transmission of the frame by the intermediate node; atthe node and during the first time interval, failing to detecttransmission of a routed acknowledgement frame from the intermediatenode to the node; retransmitting the frame from the node to theintermediate node after expiration of the first time interval; receivinga second frame at the node from the intermediate node; transmitting asecond routed acknowledgement frame from the node to the intermediatenode; at the node and during a second time interval, failing to detecttransmission of the second routed acknowledgement frame by theintermediate node; and retransmitting the second routed acknowledgementframe from the node to the intermediate node after expiration of thesecond time interval.
 13. The method of claim 12, wherein the first timeinterval includes a randomly generated time interval.
 14. The method ofclaim 12, wherein the second time interval includes a randomly generatedtime interval.
 15. The method of claim 12, wherein transmitting includesunicast transmitting.
 16. The method of claim 12, wherein retransmittingincludes unicast retransmitting.
 17. The method of claim 12, whereineach of the node and the intermediate node includes a mesh network nodein a wireless mesh network, and wherein the transmitting,retransmitting, and receiving all occur wirelessly within the wirelessmesh network.
 18. A system comprising: a mesh network node adapted totransmit a frame, to detect transmission of the frame, to retransmit theframe after failing to detect transmission of the frame during a firsttime interval, to receive a second frame, to transmit a routedacknowledgement frame in response to receiving the second frame, todetect transmission of the routed acknowledgement frame, and toretransmit the routed acknowledgement frame after failing to detecttransmission of the routed acknowledgement frame during a second timeinterval, wherein the mesh network node retransmits the frame to anintermediate node after both failing to detect transmission of the frameby the intermediate node during the first time interval and failing toreceive a routed acknowledgement frame from the intermediate node duringthe first time interval.
 19. The system of claim 18, wherein the firsttime interval includes a randomly generated time interval.
 20. Thesystem of claim 18, wherein the second time interval includes a randomlygenerated time interval.
 21. The system of claim 18, wherein the frameincludes a unicast frame.
 22. The system of claim 18, wherein the routedacknowledgement frame includes a unicast routed acknowledgement frame.